Area-time efficient systolic architecture for the DCT

被引：0
|
作者：
Meher, PK [1 ]
机构：
[1] Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore
来源：
ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS | 2005年 / 3740卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A reduced-complexity algorithm and its systolic architecture are presented for computation of the discrete cosine transform. The proposed scheme not only leads to a fully-pipelined regular and modular hardware, but also offers significantly higher throughput, lower latency and lower area-time complexity over the existing structures. The proposed design is devoid of complicated input/output mapping and complex control structure. Moreover, it does not have any restriction on the transform-length and it is easily scalable for higher transform-length as well.
引用
收藏
页码：787 / 794
页数：8
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