Design & simulation of a high performance rail-to-rail CMOS op-amp at ± 3V supply

被引：0
|
作者：
Bhaskaran, M [1 ]
Sriram, S [1 ]
Stojcevski, A [1 ]
Zayegh, A [1 ]
机构：
[1] Victoria Univ Technol, Sch Elect Engn, POB 14428, Melbourne, Vic 8001, Australia
来源：
DELTA 2006: THIRD IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS | 2006年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The paper discusses a CMOS operational amplifier at +/- 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using Cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with Slew Rate of 49.24 V/mu s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.
引用
收藏
页码：219 / +
页数：2
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