共 50 条
- [1] LegUp: High-Level Synthesis for FPGA-Based Processor/Accelerator Systems [J]. FPGA 11: PROCEEDINGS OF THE 2011 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, 2011, : 33 - 36
- [2] Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis [J]. 2014 12TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND UBIQUITOUS COMPUTING (EUC 2014), 2014, : 120 - 129
- [3] Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems [J]. APPLIED RECONFIGURABLE COMPUTING. ARCHITECTURES, TOOLS, AND APPLICATIONS, ARC 2024, 2024, 14553 : 19 - 32
- [4] High-Level Synthesis for the Design of FPGA-based Signal Processing Systems [J]. 2009 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION, PROCEEDINGS, 2009, : 25 - +
- [5] Leveraging Open Source Platforms and High-Level Synthesis for the Design of FPGA-Based 10 GbE Active Network Probes [J]. 2015 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2015,
- [6] POWER/AREA ANALYSIS OF A FPGA-BASED OPEN-SOURCE PROCESSOR USING PARTIAL DYNAMIC RECONFIGURATION [J]. 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, : 592 - 598
- [7] Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration [J]. FPGA 10, 2010, : 59 - 68
- [8] A High-Level Tool for Enhancing the Performance and Scalability of Open-Source Relational Databases [J]. 9TH INTERNATIONAL CONFERENCE ON MANAGEMENT OF EMERGENT DIGITAL ECOSYSTEMS (MEDES 2017), 2017, : 73 - 80
- [9] Optimization of FPGA-based LDPC decoder using high-level synthesis [J]. PROCEEDINGS OF THE 4TH INTERNATIONAL CONFERENCE ON COMMUNICATION AND INFORMATION PROCESSING (ICCIP 2018), 2018, : 256 - 259