An Automated Design Methodology for FPGA-based Multi-Gbps LDPC Decoders

被引：0

作者：

Duc Minh Pham ^{[1
]}

Aziz, Syed Mahfuzul ^{[1
]}

机构：

[1] Univ South Australia, Sch Elect & Informat Engn, Mawson Lakes, Australia

来源：

2012 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY (ICCIT) | 2012年

关键词：

Error correction coding; wireless communication; digital communication; design automation; digital system; FPGA;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However hardware implementation of LDPC decoders using traditional hardware description language (HDL) based approach is a complex and time consuming task. This paper presents an efficient automated high level approach to designing LDPC decoders using a collection of high level modelling tools. High data rate Multi-Gbps LDPC decoders have been developed and implemented on FPGA using the proposed methodology. These Multi-Gbps LDPC decoders can be utilized in the latest generation of high data rate wireless communication such as WLAN, WiMAX and DVB-S2.

引用

页码：495 / 499

页数：5

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