A Logic-Based Embedded DRAM with Novel Cell Structure and Dynamically Adaptive Refresh for Long Data Retention, Zero Data Availability Penalty and High Yield

被引：0

作者：

Xue, X. Y. ^{[1
]}

Meng, C. ^{[1
]}

Dong, C. L. ^{[1
]}

Chen, B. ^{[1
]}

Lin, Y. Y. ^{[1
]}

Huang, R. ^{[2
]}

Zou, Q. T. ^{[2
]}

Wu, J. G. ^{[2
]}

机构：

[1] Fudan Univ, ASIC & Syst State Key Lab, Shanghai 201203, Peoples R China

[2] Semiconduct Mfg Int Corp, Technol Res & Dev Ctr, Shanghai, Peoples R China

来源：

2013 5TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW) | 2013年

关键词：

embedded DRAM; refresh; retention;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Three techniques are proposed and verified on a logic-based 128kb embedded DRAM macro. Novel 2T gain cell of asymmetric junction increases data retention by 21X. Dynamically adaptive staggered refresh achieves zero data availability penalty and improves yield significantly. 60% smaller cell size than 6T SRAM and 25-30% refresh power reduction are obtained.

引用

页码：132 / 134

页数：3