Design and implementation of a workload specific simulator

This paper proposes a simple but efficient technique for instruction set simulators. Our simulator is made workload specific by a simple process to generate a set of C functions from a workload binary It is as portable and retargetable as ordinary instruction emulators because the translation targets C code and works well with well-abstracted instruction definitions. The translation is also easy-to-implement without requiring any complicated analysis nor profiling. We also propose a set of simple optimization techniques for cache simulation which cooperates with the workload specific technique. A SimpleScalar-based implementation of these techniques results a significantly large performance improvement. Our evaluations with SPEC CPU95 exhibit that the maximum speedups over sim-fast, sim-cache and sim-outorder are 38-fold, 14-fold and 9.7-fold respectively, while the average numbers are 19-fold, 8.3-fold and 3.8-fold.