A unified approach for verification and validation of systems and software engineering models

被引：7
|
作者：
Alawneh, Luay [1 ]
Debbabi, Mourad [1 ]
Hassaine, Fawzi [2 ]
Jarraya, Yosr [1 ]
Soeanu, Andrei [1 ]
机构：
[1] Concordia Univ, Concordia Inst Informat Syst Engn, Comp Secur Lab, Montreal, PQ, Canada
[2] Def Res & Dev Canada, Future Forces Synthet Environm Sect, Ottawa, ON, Canada
来源：
13TH ANNUAL IEEE INTERNATIONAL SYMPOSIUM AND WORKSHOP ON ENGINEERING OF COMPUTER BASED SYSTEMS, PROCEEDINGS: MASTERING THE COMPLEXITY OF COMPUTER-BASED SYSTEMS | 2006年
关键词：
D O I：
10.1109/ECBS.2006.17
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm relies on an established synergy between three salient approaches, which are model-checking, program analysis, and software engineering techniques. To illustrate the accomplishment of our results, we have designed and implemented an integrated and automated computer-aided assessment tool. We provide three case studies for sequence, state machine, and class and package diagrams to demonstrate the benefits of our methodology.
引用
收藏
页码：409 / +
页数：2
相关论文
共 50 条
  • [1] Synergistic verification and validation of systems and software engineering models
    Jarraya, Yosr
    Soeanu, Andrei
    Alawneh, Luay
    Debbabi, Mourad
    Hassaine, Fawzi
    [J]. INTERNATIONAL JOURNAL OF GENERAL SYSTEMS, 2009, 38 (07) : 719 - 746
  • [2] The Verification and Validation of Embedded Systems using Cleanroom Software Engineering
    Gao Guohong
    Zhang Baojian
    Li Xueyong
    [J]. NANOTECHNOLOGY AND COMPUTER ENGINEERING, 2010, 121-122 : 922 - 928
  • [3] Unified software method: an engineering approach to software engineering
    Mercier, Stephane
    Lavoie, Michel
    Champagne, Roger
    [J]. 30TH ANNUAL IEEE/NASA SOFTWARE ENGINEERING WORKSHOP, PROCEEDINGS, 2006, : 89 - +
  • [4] Software verification and validation within the (rational) unified process
    Fuhrman, C
    Djlive, F
    Palza, E
    [J]. 28TH ANNUAL NASA GODDARD SOFTWARE ENGINEERING WORKSHOP, PROCEEDINGS, 2004, : 216 - 220
  • [5] VALIDATION AND VERIFICATION OF SOFTWARE PROCESS MODELS
    GRUHN, V
    [J]. LECTURE NOTES IN COMPUTER SCIENCE, 1991, 509 : 271 - 286
  • [6] A component-based approach to verification and validation of formal software models
    Desovski, Dejan
    Cukic, Bojan
    [J]. ARCHITECTING DEPENDABLE SYSTEMS IV, 2007, 4615 : 89 - +
  • [7] The Verification and Validation of Software Architecture for Systems of Systems
    Michael, James Bret
    Riehle, Richard
    Sling, Man-Tak
    [J]. 2009 IEEE INTERNATIONAL CONFERENCE ON SYSTEM OF SYSTEMS ENGINEERING SOSE 2009, 2009, : 130 - 135
  • [8] A Unified Approach to Requirements Validation and System Verification
    Foster, George J.
    Helm, Annette L.
    [J]. 2010 IEEE INTERNATIONAL SYSTEMS CONFERENCE, 2010, : 404 - 408
  • [9] Verification and Validation for Trustworthy Software Systems
    Michael, James Bret
    Drusinsky, Doron
    Otani, Thomas W.
    Shing, Man-Tak
    [J]. IEEE SOFTWARE, 2011, 28 (06) : 86 - 92
  • [10] An architectural approach to the analysis, verification and validation of software intensive embedded systems
    DeJiu Chen
    Lei Feng
    Tahir Naseer Qureshi
    Henrik Lönn
    Frank Hagl
    [J]. Computing, 2013, 95 : 649 - 688
12345