From UML State Machines to Verifiable Lotos Specifications

被引:0
|
作者
Babaee, Reza [1 ]
Babamir, Seyed Morteza [1 ]
机构
[1] Univ Kashan, Kashan, Iran
来源
INNOVATIVE COMPUTING TECHNOLOGY | 2011年 / 241卷
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中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
The theoretical prospect of Formal specification languages has been improved during last years. The pragmatic aspects of the formal methods has been scrutinized especially in the safety-critical systems. However there still remains a constant fear among industry practitioners to work with purely theoretical specification methods even though their software system operates in highly safety-critical applications. We propose a hands-on approach in order to gradually transform popular UML 2.0 State Machines (SM) to verifiable Lotos specifications. In this algorithm the partial logical view of the system,represented by the UML 2.0 SM, would be converted to verifiable Basic Lotos specification, it then may be developed as an executable program to mechanize the transformation.
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页码:121 / 129
页数:9
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