An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation

被引：0
|
作者：
Huang, Wei-pei [1 ]
Cheung, Ray C. C. [1 ]
Yan, Hong [1 ]
机构：
[1] City Univ Hong Kong, Dept Elect Engn, Hong Kong, Peoples R China
来源：
2019 IEEE 30TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2019) | 2019年
关键词：
tensor computation; ASIP; hardware architecture; field-programmable gate array (FPGA);
D O I：
10.1109/ASAP.2019.00-36
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In the past decade, tensor computation is widely used in different areas. Various software toolbox have been released to assist tensor computation. However, there is still no hardware architecture to accelerate the tensor computation. This paper presents an efficient application specific instruction set processor (ASIP) for tensor computation. Different tensor computations are fully optimized in terms of resource usage and performance. We implement the ASIP on FPGA platform. We test our design by implementing the CANDECOMP/PARAFAC(CP) decomposition. Our design can achieve a low resource usage and run at 141 Mhz.
引用
收藏
页码：37 / 37
页数：1
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