Multilevel Switching Characteristics of Si3N4-Based Nano-Wedge Resistive Switching Memory and Array Simulation for In-Memory Computing Application

被引:5
|
作者
Lee, Dong Keun [1 ,2 ]
Kim, Min-Hwi [1 ,2 ]
Bang, Suhyun [1 ,2 ]
Kim, Tae-Hyeon [1 ,2 ]
Kim, Sungjun [3 ]
Cho, Seongjae [4 ]
Park, Byung-Gook [1 ,2 ]
机构
[1] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 08826, South Korea
[2] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 08826, South Korea
[3] Dongguk Univ, Div Elect & Elect Engn, Seoul 04620, South Korea
[4] Gachon Univ, Dept IT Convergence Engn, Gyeonggi Do 13120, South Korea
基金
新加坡国家研究基金会;
关键词
nano-wedge; resistive switching random-access memory; switching layer; TMAH; switching process; array; neural network; RESET MECHANISM; SYNAPSE DEVICE; CONDUCTANCE;
D O I
10.3390/electronics9081228
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this research, nano-wedge resistive switching random-access memory (ReRAM) based on a Si(3)N(4)switching layer and silicon bottom electrode was fabricated, and its multilevel switching characteristics were investigated. The wedge bottom electrode was formed by a tetramethyl ammonium hydroxide (TMAH) wet-etching process. The nano-wedge ReRAM was demonstrated to have different reset current levels by varying the compliance currents. To explain the effect of modulating the compliance currents, the switching characteristics of both the SET and RESET behaviors were shown. After measuring the device under four different compliance currents, it was proved to have different current levels due to an inhibited resistive state after a SET switching process. Furthermore, SPICE circuit simulation was carried out to show the effect of line resistance on current summation for the array sizes of 8 x 8 and 16 x 16. These results indicate the importance of minimizing the line resistance for successful implementation as a hardware-based neural network.
引用
收藏
页码:1 / 8
页数:8
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