AUTOMATED HARDENING OF DEEP NEURAL NETWORK ARCHITECTURES

被引：0

作者：

Beyer, Michael ^{[1
,2
]}

Schorn, Christoph ^{[2
]}

Fabarisov, Tagir ^{[3
]}

Morozov, Andrey ^{[3
]}

Janschek, Klaus ^{[1
]}

机构：

[1] Tech Univ Dresden, Inst Automat, Dresden, Germany

[2] Robert Bosch GmbH, Bosch Corp Res, Renningen, Germany

[3] Univ Stuttgart, Inst Ind Automat & Software Engn, Stuttgart, Germany

来源：

PROCEEDINGS OF ASME 2021 INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION (IMECE2021), VOL 13 | 2021年

关键词：

Neural Architecture Search; Error Resilience; Random Hardware Faults; Neural Network Hardware;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Designing optimal neural network (NN) architectures is a difficult and time-consuming task, especially when error resiliency and hardware efficiency are considered simultaneously. In our paper, we extend neural architecture search (NAS) to also optimize a NN's error resilience and hardware related metrics in addition to classification accuarcy. To this end, we consider the error sensitivity of a NN on the architecture-level during NAS and additionally incorporate checksums into the network as an external error detection mechanism. With an additional computational overhead as low as 17% for the discovered architectures, checksums are an efficient method to effectively enhance the error resilience of NNs. Furthermore, the results show that cell-based NN architectures are able to maintain their error resilience characteristics when transferred to other tasks.

引用

页数：10

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