A New VDD- and GND-Floating Rails SRAM with Improved Read SNM and without Multi-Level Voltage Regulator

This paper presents a new scheme to improve write-ability and read stability of conventional 6T SRAM cell. The proposed design for SRAM cell is similar to conventional one but with smaller (minimum size) access transistors. Using smaller size access transistors leads to improved read stability. In our design, power and ground rails of neighbouring cells in the same row of SRAM array float during write operation. As a result, improvement of Write Noise Margin (WNM) by 56% at VDD=500mV over the conventional design, approves better write-ability of our design. In this design, read operation is done at supply voltages of two times larger than VDD, resulting in higher Read SNM (RSNM) for it. A charge pump circuit is used to provide this power line for read operation. At the end, we used an architecture for integrating SRAM cells in the array that results in lower power consumption due to removed sneaky current that normally exists in previous architectures.