Power Supply Filter for PLL Circuit in Digital Systems

被引：0

作者：

Pham, Nam ^{[1
]}

Pakbaz, Faraydon ^{[1
]}

Jin, Zhenrong ^{[1
]}

Walls, Lloyd ^{[1
]}

机构：

[1] IBM Corp, Austin, TX 78758 USA

来源：

2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2014年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an effective design approach for the power supply filter of a phase lock loop (PLL) based clock generator in a multi-core ASIC. The noise sensitivity of different types, filter design, system design issues, and measurement techniques for verification and understanding of jitter behavior on power supply noise are discussed

引用

页码：535 / 540

页数：6

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