Low-k Interconnect Stack with Metal-Insulator-Metal Capacitors for 22nm High Volume Manufacturing

被引：0

作者：

Ingerly, D. ^{[1
]}

Agrawal, A. ^{[1
]}

Ascazubi, R. ^{[1
]}

Blattner, A. ^{[1
]}

Buehler, M. ^{[1
]}

Chikarmane, V. ^{[1
]}

Choudhury, B. ^{[1
]}

Cinnor, F. ^{[1
]}

Ege, C. ^{[1
]}

Ganpule, C. ^{[1
]}

Glassman, T. ^{[1
]}

Grover, R. ^{[1
]}

Hentges, P. ^{[1
]}

Hicks, J. ^{[2
]}

Jones, D. ^{[1
]}

Kandas, A. ^{[1
]}

Khan, H. ^{[1
]}

Lazo, N. ^{[1
]}

Lee, K. S. ^{[1
]}

Liu, H. ^{[1
]}

Madhavan, A. ^{[1
]}

McFadden, R. ^{[1
]}

Mule', T. ^{[1
]}

Parsons, D. ^{[1
]}

Parthangal, P. ^{[1
]}

Rangaraj, S. ^{[2
]}

Rao, D. ^{[1
]}

Roesler, J. ^{[1
]}

Schmitz, A. ^{[2
]}

Sharma, M. ^{[1
]}

Shin, J. ^{[1
]}

Shusterman, Y. ^{[1
]}

Speer, N. ^{[1
]}

Tiwari, P. ^{[3
]}

Wang, G. ^{[3
]}

Yashar, P. ^{[1
]}

Mistry, K. ^{[1
]}

机构：

[1] Intel Corp, Logic Technol Dev, 5200 NE Elam Young Pkwy, Hillsboro, OR 97229 USA

[2] Intel Corp, Corp Qual Network, Hillsboro, OR 97229 USA

[3] Intel Corp, Assembly Test & Technol Dev, Hillsboro, OR 97229 USA

来源：

2012 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC) | 2012年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13-18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.

引用

页数：3

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