Reduction of silicon waveguide endface reflection using a taper

被引:0
|
作者
Chen, Qian [1 ,2 ]
Zhou, Xin [1 ,2 ]
Wang, Ying [1 ,2 ]
Huang, Qingzhong [3 ]
Chen, Xiangning [2 ,4 ]
Jiang, Wei [1 ,2 ]
机构
[1] Nanjing Univ, Coll Engn & Appl Sci, Nanjing 210093, Jiangsu, Peoples R China
[2] Natl Lab Solid State Microstruct, Nanjing 210093, Jiangsu, Peoples R China
[3] Huazhong Univ Sci & Technol, Wuhan Natl Lab Optoelect, Wuhan 430074, Peoples R China
[4] Nanjing Univ, Coll Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China
关键词
silicon waveguide endface reflection (SWER); inverse taper; silicon photonics SOI; 3D-FDTD; DC; SINGLE-MODE FIBER;
D O I
10.1117/12.2293286
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
In this paper, a method that adds an inverse taper at the endface of the waveguide is analyzed to reduce the silicon waveguide endface reflection (SWER). A high index-contrast optical waveguide on a silicon-on-insulator (SOI) wafer allows for the strong optical confinement, while it also brings in a substantial endface reflection. Most parameters of the taper, such as the length and tip width of the taper, and wavelength of the guided light, even the shape of the taper, have been studied in detail using the three-dimensional finite-difference time-domain (3D-FDTD) method to reduce the SWER. In addition, we have also proposed a new structure that adds the special taper to the straight-through port of the 3-dB directional coupler (DC) to measure the SWER in experiments. The experimental results show good agreement with our simulation results. This taper is useful and small enough that can be applied to many silicon photonic devices and large scale photonic integration circuits (PICs).
引用
收藏
页数:8
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