High-level synthesis through transforming VHDL models

被引：0
|
作者：
Prihozhy, A [1 ]
机构：
[1] Belarussian State Polytech, Minsk, BELARUS
来源：
SYSTEM-ON-CHIP METHODOLOGIES & DESIGN LANGUAGES | 2001年
关键词：
high-level synthesis; VHDL; behavioral model transformation; scheduling; allocation; binding; design space exploration;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper a method of transforming a behavioral VHDL-model to a functionally equivalent model with one basic block is proposed. High-level synthesis techniques including scheduling, allocation, and binding are modified for the model. These reduce the number of control steps, FSM states, state transitions, functional and storage units in an RTL-structure.
引用
收藏
页码：135 / 146
页数：12
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