A bit-interleaved systolic architecture for a high-speed RSA system

被引：2

作者：

Pekmestzi, KZ ^{[1
]}

Moshopoulos, NK ^{[1
]}

机构：

[1] Natl Tech Univ Athens, Dept Elect & Comp Engn, Athens 15773, Greece

来源：

INTEGRATION-THE VLSI JOURNAL | 2001年 / 30卷 / 02期

关键词：

systolic circuit; Montgomery; RSA; square and multiply;

D O I：

10.1016/S0167-9260(01)00017-7

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new systolic serial-parallel scheme that implements the Montgomery multiplier is presented. The serial input of this multiplier consists of two sets of data that enter in a bit-interleaved form. The results are also derived in the same form. The design, with minor modifications, can be used for the implementation of the RSA algorithm by realizing the square-and-multiply algorithm. The circuit yields the lowest hardware complexity reported and permits high-speed operation with 100% efficiency. (C) 2001 Elsevier Science B.V. All rights reserved.

引用

页码：169 / 175

页数：7

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