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- [1] Computation Reduction for Statistical Analysis of the Effect of nano-CMOS Variability on Asynchronous Circuits PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2010, : 161 - 166
- [3] Impact analysis of statistical variability on the accuracy of a propagation delay time compact model in nano-CMOS technology Journal of Computational Electronics, 2018, 17 : 192 - 204
- [5] A unified statistical model for inter-die and intra-die process variation SISPAD: 2005 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2005, : 131 - 134
- [6] On statistical timing analysis with inter- and intra-die variations DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 132 - 137
- [7] Exploiting correlation kernels for efficient handling of intra-die spatial correlation, with application to statistical timing 2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 735 - 740
- [8] Statistical timing analysis for intra-die process variations with spatial correlations ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2003, : 900 - 907
- [9] Statistical clock skew analysis considering intra-die process variations ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2003, : 914 - 921
- [10] Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits 2009 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2009, : 99 - 102