A DISCREPANCY-COMPUTATIONLESS RiBM ALGORITHM AND ITS ARCHITECTURE FOR BCH DECODERS

被引：2
|
作者：
Yoon, Sangho [1 ]
Lee, Hanho [1 ]
机构：
[1] Inha Univ, Dept Informat & Commun Engn, Inchon 402751, South Korea
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2008年
关键词：
D O I：
10.1109/SOCC.2008.4641549
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a novel Discrepancy Computationless RiBM (DcRiBM) algorithm and its architecture for decoding BCH codes. The DcRiBM algorithm allows elimination of the discrepancy computation control block and reduced hardware complexity as compared to conventional RiBM algorithm architecture. The low-complexity DcRiBM architecture has been designed and implemented with 0.18-mu m CMOS standard cell technology in a supply voltage of 1.8 V. The BCH(2040,1930) decoder with the proposed architecture operates approximately 2.9 Gb/s at a clock frequency of 265 MHz and has approximately 32% fewer gate counts than the conventional RiBM architecture.
引用
收藏
页码：379 / 382
页数：4
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