Random Interface Trap Induced Fluctuation in 22nm High-k/Metal Gate Junctionless and Inversion-mode FinFETs

被引：0
|
作者：
Wang, Yijiao [1 ]
Wei, Kangliang [1 ]
Liu, Xiaoyan [1 ]
Du, Gang [1 ]
Kang, Jinfeng [1 ]
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
来源：
2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA) | 2013年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The impact of random interface trap (RIT) on the junctionless MOSFET (JL-FET) is investigated. Both acceptor-like and donor-like interface traps are considered to 22nm high-k metal gate (HKMG) junctionless structure and traditional inversion-mode FinFET. Fluctuations in threshold voltage, on current, leakage current, drain induced barrier lowering and subthreshold swing are analyzed. The results show that the position effect and type of interface traps (ITs) can induce different fluctuation for JL-FET and FinFET.
引用
收藏
页数：2
相关论文
共 50 条
  • [1] Dual Channel FinFETs as a Single High-k/Metal Gate Solution Beyond 22nm Node
    Smith, C. E.
    Adhikari, H.
    Lee, S-H.
    Coss, B.
    Parthasarathy, S.
    Young, C.
    Sassman, B.
    Cruz, M.
    Hobbs, C.
    Majhi, P.
    Kirsch, P. D.
    Jammy, R.
    2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 284 - +
  • [2] Impact of Random Interface Traps and Random Dopants in High-k/Metal Gate Junctionless FETs
    Wang, Yijiao
    Huang, Peng
    Wei, Kangliang
    Zeng, Lang
    Liu, Xiaoyan
    Du, Gang
    Zhang, Xing
    Kang, Jinfeng
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2014, 13 (03) : 584 - 588
  • [3] Application of Taguchi Method in Designing a 22nm High-k/Metal Gate NMOS Transistor
    Maheran, Afifah A. H.
    Menon, P. S.
    Ahmad, I.
    Shaari, S.
    MICRO/NANO SCIENCE AND ENGINEERING, 2014, 925 : 514 - +
  • [4] Gate first band edge high-k/metal stacks with EOT=0.74nm for 22nm node nFETs
    Huang, J.
    Kirsch, P. D.
    Hussain, M.
    Heh, D.
    Sivasubramani, P.
    Young, C.
    Gilmer, D. C.
    Park, C. S.
    Tan, Y. N.
    Park, C.
    Harris, H. R.
    Majhi, P.
    Bersuker, G.
    Lee, B. H.
    Tseng, H. -H.
    Jammy, R.
    2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM, 2008, : 152 - +
  • [5] Aging-Aware Adaptive Voltage Scaling in 22nm High-K/Metal-Gate Tri-Gate CMOS
    Cho, Minki
    Tokunaga, Carlos
    Khellah, Muhammad M.
    Tschanz, James W.
    De, Vivek
    2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2015,
  • [6] Integration Challenges and Options of Replacement High-k/Metal Gate Technology for (Sub-)22nm Technology Nodes
    Veloso, A.
    Ragnarsson, L. -A.
    Schram, T.
    Chew, S. A.
    Boccardi, G.
    Thean, A.
    Horiguchi, N.
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2013 (CSTIC 2013), 2013, 52 (01): : 385 - 390
  • [7] Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs
    Dai, Liang
    Lu, Weifeng
    Lin, Mi
    ELECTRONICS, 2019, 8 (03):
  • [8] Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor
    Maheran, Afifah A. H.
    Menon, P. S.
    Ahmad, I.
    Shaari, S.
    Elgomati, H. A.
    Salehuddin, F.
    3RD ISESCO INTERNATIONAL WORKSHOP AND CONFERENCE ON NANOTECHNOLOGY 2012 (IWCN2012), 2013, 431
  • [9] Issues on Interfacial Oxide Layer (IL) in EOT Scaling of High-k/Metal Gate CMOS for 22nm Technology Node and Beyond
    Park, C. S.
    Kirsch, P. D.
    PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 8, 2010, 33 (03): : 45 - 52
  • [10] Impact of Trap Behavior on Random Telegraph Noise in High-k/Metal Gate pMOSFETs
    Kao, Tsung-Hsien
    Chang, Sheng-Po
    Chang, Shoou-Jinn
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2018, 13 (04) : 454 - 457
12345