On statistical correlation based path selection for timing validation

This paper presents a path selection methodology based on statistical timing models. Our contributions are twofold: (1) Unlike previous works in statistical path selection [1, 2] where path set quality was analyzed using a pattern-independent static approach, this work analyzes the quality of patterns generated from the selected paths. (2) Unlike in previous works where the timing model is assumed to be 100% accurate, our path selection strategy aims to tolerate inaccurate timing models. To achieve pattern-based analysis, we develop an efficient timing simulator that can model both inter-die and intra-die process variations. To accomplish error tolerance in timing models, we introduce the concept of Universal Representative Path Set (UR-Set). We present experimental results to illustrate the usage of the statistical timing simulator and to demonstrate the superiority of our path selection methodology based on benchmark circuits.