A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS

被引：6

作者：

Gangasani, Gautam R. ^{[1
]}

Kinget, Peter R. ^{[1
]}

机构：

[1] Columbia Univ, Dept Elect Engn, New York, NY 12524 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2019年 / 66卷 / 05期

关键词：

Sub-integer; frequency synthesizer; injection-locked ring oscillator; programmable divider; DIVIDER; PLL;

D O I：

10.1109/TCSII.2019.2910075

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 9-GHz sub-integer frequency synthesizer incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5 V, phase-switching-based programmable division for sub-integer frequency synthesis, and automatic calibration to ensure injection lock. The synthesizer consumes 3.5 mW of power at 9.12 GHz and 0.05 mm(2) of area, while showing an output phase noise of -100 dBc/Hz at 1 MHz offset and RMS jitter of 325 fs; it achieves a net FOMA of -186.5 in a 45-nm SOI CMOS process.

引用

页码：803 / 807

页数：5