High-Performance Silicon Nanotube Tunneling FET for Ultralow-Power Logic Applications

被引：84

作者：

Fahad, Hossain M. ^{[1
]}

Hussain, Muhammad M. ^{[1
]}

机构：

[1] King Abdullah Univ Sci & Technol, Integrated Nanotechnol Lab, Elect Engn Program, Comp Elect Math Sci & Engn Div, Thuwal 239556900, Saudi Arabia

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2013年 / 60卷 / 03期

关键词：

BTBT; high performance; nanotube (NT); silicon; FIELD-EFFECT TRANSISTORS;

D O I：

10.1109/TED.2013.2243151

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow OFF-state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs.

引用

页码：1034 / 1039

页数：6

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