AN ENERGY-EFFICIENT MEMORY-BASED HIGH-THROUGHPUT VLSI ARCHITECTURE FOR CONVOLUTIONAL NETWORKS

被引:0
|
作者
Kang, Mingu
Gonugondla, Sujan K.
Keel, Min-Sun
Shanbhag, Naresh R.
机构
关键词
Compute memory; Convolutional networks; Machine learning; Pattern recognition;
D O I
暂无
中图分类号
O42 [声学];
学科分类号
070206 ; 082403 ;
摘要
In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory (CM) [1], where computation is deeply embedded into the memory (SRAM). Behavioral models incorporating CM's circuit non-idealities and energy models in 45 nm SOI CMOS are presented. System-level simulations using these models demonstrate that the probability of handwritten digit recognition P-r > 0.99 can be achieved using the MNIST database [2], along with a 24.5 x reduced energy delay product, a 5.0 x reduced energy, and a 4.9 x higher throughput as compared to the conventional system.
引用
收藏
页码:1037 / 1041
页数:5
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