A Case Study of Hierarchical Diagnosis for Core-Based SoC

被引：0

作者：

Wang, Eric ^{[1
]}

Huang, Yu ^{[2
]}

Cheng, Wu-Tung ^{[2
]}

Yang, Wu ^{[2
]}

Fu, James ^{[2
]}

机构：

[1] Freescale Semicond, 288 ZhuYuan Rd, Suzhou 215011, Jiangsu, Peoples R China

[2] Mentor Graph Corp, Wilsonville, OR 97070 USA

来源：

CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2010 (CSTIC 2010) | 2010年 / 27卷 / 01期

关键词：

D O I：

10.1149/1.3360617

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

In this paper, a silicon debug case study was given in the context of a hierarchical diagnosis flow for core-based SoC. We discuss (1) how to design a simple core wrapper that supports at-speed test, (2) how to map the failures collected from the chip level to core level, and (3) how to perform failure analysis and silicon debug under the guidance of diagnosis results.

引用

页码：185 / 190

页数：6

共 50 条

[1] On Concurrent Test of Core-Based SOC Design
Yu Huang
Wu-Tung Cheng
Chien-Chung Tsai
Nilanjan Mukherjee
Omer Samman
Yahya Zaidan
Sudhakar M. Reddy
Journal of Electronic Testing, 2002, 18 : 401 - 414
[2] On concurrent test of core-based SOC design
Huang, Y
Cheng, WT
Tsai, CC
Mukherjee, N
Samman, O
Zaidan, Y
Reddy, SM
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2002, 18 (4-5): : 401 - 414
[3] Efficient Testing of Hierarchical Core-Based SOCs
Keller, B.
Chakravadhanula, K.
Foutz, B.
Chickermane, V.
Garg, A.
Schoonover, R.
Sage, J.
Pearl, D.
Snethen, T.
2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2014,
[4] Core-based SoC test scheduling using evolutionary algorithm
Xia, Y
Chrzanowska-Jeske, M
Wang, B
CEC: 2003 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-4, PROCEEDINGS, 2003, : 1716 - 1723
[5] A new core-based method for hierarchical incremental clustering
Serban, G
Câmpan, A
SEVENTH INTERNATIONAL SYMPOSIUM ON SYMBOLIC AND NUMERIC ALGORITHMS FOR SCIENTIFIC COMPUTING, PROCEEDINGS, 2005, : 77 - 82
[6] IEEE Std 1500 enables core-based SoC test development
Cheng, Tim
IEEE DESIGN & TEST OF COMPUTERS, 2009, 26 (01): : 4 - 4
[7] Core-Based Testing of Embedded Mixed-Signal Modules in a SoC
Zivkovic, Vladimir A.
Schat, Jan
van der Heyden, Frank
Seuren, Geert
IEEE DESIGN & TEST OF COMPUTERS, 2009, 26 (03): : 78 - 86
[8] Scalable core-based methodology and synthesizable core for systematic design environment in multicore SoC (MCSoC)
Abderazek, Ben A.
Yoshinaga, Tsutomu
Sowa, Masahiro
2006 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, PROCEEDINGS, 2006, : 345 - +
[9] Resource allocation and test scheduling for concurrent test of core-based SOC design
Huang, Y
Cheng, WT
Tsai, CC
Mukherjee, N
Samman, O
Zaidan, Y
Reddy, SM
10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 265 - 270
[10] Optimization of Core-based SOC Test Scheduling based on Modified Differential Evolution Algorithm
Deng Libao
Wei Debao
Qiao Liyan
Bian Xiaolong
Zhang Baoquan
2016 IEEE AUTOTESTCON PROCEEDINGS, 2016,

← 1 2 3 4 5 →