A new test generation approach for embedded analogue cores in SoC

被引：2

作者：

Stancic, M ^{[1
]}

Fang, L ^{[1
]}

Weusthof, MHH ^{[1
]}

Tijink, RMW ^{[1
]}

Kerkhoff, HG ^{[1
]}

机构：

[1] Univ Twente, Testable Design & Testing Microsyst Grp, MESA & Res Inst, NL-7500 AE Enschede, Netherlands

来源：

INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/TEST.2002.1041840

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a new test-generation approach for embedded analogue cores in SoC Die key features of this approach are the developed testability-analysis based multi-frequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DfT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

引用

页码：861 / 869

页数：9

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