Feasibility of plasmonic circuits for on-chip interconnects

Feasibility of fabricating plasmonic circuits by complementary metal-oxidesemiconductor (CMOS) compatible processes is presented, and the circuit performances are numerically and experimentally discussed from the viewpoint of operating speed and energy loss. The transmission speed of plasmonic signals, which is governed by the dispersion of circuits, is calculated to be about two orders of magnitude higher than that of electric signals. The energy loss per single transmitted-bit is estimated using shot-noise limits, and it is clarified that plasmonic signals are superior to electric ones if the transmitted distance is set to an area within a few hundred micrometers. Based on these results and the experimental results of each plasmonic components, the feasibility of plasmonic circuits are demonstrated. In addition, the feasibility of the functional expansion of plasmonic circuits, such as wavelength-division-multiplexing networks, is discussed using experimental values of plasmonic components fabricated by CMOS-compatible processes. These plasmonic circuits and networks can be merged into silicon integrated circuits on a silicon substrate using CMOS compatible processes.