A DLL-BASED FRACTIONAL-N FREQUENCY SYNTHESIZER WITH A PROGRAMMABLE INJECTION CLOCK

被引:0
|
作者
Guo, Haizheng [1 ]
Kwasniewski, Tad [1 ]
机构
[1] Carleton Univ, Ottawa, ON K1S 5B6, Canada
关键词
delay-locked loop; digital-to-phase converter; fractioanal-N frequency synthesizer; DELAY-LOCKED LOOP;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
A delay-locked loop (DLL) based fractional-N frequency synthesizer with a programmable injection clock is presented. The proposed DLL architecture overcomes the integer-N limitation of the conventional DLL-based frequency multiplier, and can achieve small frequency step while maintaining low jitter accumulation. The frequency multiplication part is achieved by using either edge-combing DLL or MDLL structure, while the programmable injection clock is obtained by employing a DLL-based digital-to-phase converter. Based on the proposed architecture, a frequency synthesizer with 50MHz-1.3GHz output frequency tuning range has been design in 0.18 mu m CMOS technology. And a multiplication ratio of MN / (N+k) can be obtained, in which M, N and K are programmable. The DLL achieves around -42dB reference spur level.
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页数:4
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