Amorphous oxide semiconductor memory using high-k charge trap layer

被引:0
|
作者
Rha, S. -H. [1 ,2 ,4 ]
Jung, J. S. [1 ,2 ]
Kim, J. H. [1 ,2 ]
Kim, U. K. [1 ,2 ]
Chung, Y. J. [1 ,2 ]
Jung, H. -S [1 ,2 ]
Lee, S. Y. [3 ]
Hwang, C. S. [1 ,2 ]
机构
[1] Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
[2] Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South Korea
[3] Samsung Adv Inst Technol, Display Device & Proc Lab, Gyeonggido 446712, South Korea
[4] Samsung Elect Co Ltd, Semicond R& Ctr, Proc Dev Team, Gyeonggido 446712, South Korea
来源
THIN FILM TRANSISTORS 10 (TFT 10) | 2010年 / 33卷 / 05期
基金
新加坡国家研究基金会;
关键词
D O I
10.1149/1.3481260
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
Amorphous oxide semiconductor memory devices with HfInZnOx as the channel layer and high-k dielectric stacks as the charge storage medium were fabricated. HfO2 and Al2O3 and HfAlOx films were examined as the charge trap layers. The drain current - gate voltage transfer curves of the fabricated charge trap memories shows a large hysteresis due to the electron trapping and de-trapping at the interfaces between the high-k charge storage layer and the SiO2. The device structure and operational scheme for the amorphous oxide semiconductor charge trap memories were suggested based on these properties.
引用
收藏
页码:375 / 380
页数:6
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