Amorphous oxide semiconductor memory using high-k charge trap layer
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Rha, S. -H.
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Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South Korea
Samsung Elect Co Ltd, Semicond R& Ctr, Proc Dev Team, Gyeonggido 446712, South KoreaSeoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Rha, S. -H.
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Jung, J. S.
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Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South KoreaSeoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Jung, J. S.
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Kim, J. H.
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Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South KoreaSeoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Kim, J. H.
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Kim, U. K.
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Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South KoreaSeoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Kim, U. K.
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Chung, Y. J.
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Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South KoreaSeoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Chung, Y. J.
[1
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Jung, H. -S
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Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South KoreaSeoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Jung, H. -S
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Lee, S. Y.
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Samsung Adv Inst Technol, Display Device & Proc Lab, Gyeonggido 446712, South KoreaSeoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Lee, S. Y.
[3
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Hwang, C. S.
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Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South KoreaSeoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
Hwang, C. S.
[1
,2
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机构:
[1] Seoul Natl Univ, Dept Mat Sci & Engn, WCU Hybrid Mat Program, Seoul 151744, South Korea
[2] Seoul Natl Univ, Inter Univ Semicond Res Ctr, Seoul 151744, South Korea
[3] Samsung Adv Inst Technol, Display Device & Proc Lab, Gyeonggido 446712, South Korea
[4] Samsung Elect Co Ltd, Semicond R& Ctr, Proc Dev Team, Gyeonggido 446712, South Korea
Amorphous oxide semiconductor memory devices with HfInZnOx as the channel layer and high-k dielectric stacks as the charge storage medium were fabricated. HfO2 and Al2O3 and HfAlOx films were examined as the charge trap layers. The drain current - gate voltage transfer curves of the fabricated charge trap memories shows a large hysteresis due to the electron trapping and de-trapping at the interfaces between the high-k charge storage layer and the SiO2. The device structure and operational scheme for the amorphous oxide semiconductor charge trap memories were suggested based on these properties.