A low complexity Reed-Solomon architecture using the Euclid's algorithm

This paper describes an efficient pipelined Reed-Solomon (RS) decoder. The proposed RS decoder architecture is based on the Euclid's algorithm, which can reduce the hardware complexity by more than 16% of existing RS architecture. The proposed RS decoder can be programmed to decode four RS codes defined in Galois field 2(8), i.e., (200, 188), (120, 108), (60, 48), and (40, 28) and can correct up to six errors. We have developed VHDL models and performed logic synthesis using the SYNOPSYS(TM) CAD tool. We have used the SAMSUNG(TM) 0.6 mu m SOG (Sea-of-Gate) cell library (KG75000). The total number of gates is about 31,000 and the proposed RS decoder operates at 40 MHz for the worst case simulations.