A 4-40 Gb/s PAM4 Transmitter with Output Linearity Optimization in 65 nm CMOS

被引：0

作者：

Zheng, Xuqiang ^{[1
,2
]}

Zhang, Chun ^{[1
]}

Lv, Fangxu ^{[1
]}

Zhao, Feng ^{[2
]}

Yue, Shigang ^{[2
]}

Wang, Ziqiang ^{[1
]}

Li, Fule ^{[1
]}

Jiang, Hanjun ^{[1
]}

Wang, Zhihua ^{[1
]}

机构：

[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China

[2] Univ Lincoln, Sch Comp Sci, Lincoln LN6 7TS, England

来源：

2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 4-40 Gb/s current mode PAM4 transmitter with an optimized eye linearity. By embedding an additional mixed combiner and an extra current source into the output driver and developing a coherent scaled-replica based bias generator, the channel-length modulation caused tail-current variations for both DC and AC coupling modes can be effectively compensated. Implemented in 65 nm CMOS, the transmitter occupies an area of 1.02 mm(2) and consumes 102 mW at 40 Gb/s. After applying the proposed linearity optimization, the measured eye linearity can be optimized from 1.28 to 1.01 with a single-end swing of 480 mV in AC coupling mode.

引用

页数：4

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