The Study on RF Front-End Circuit Design Based on Low-Noise Amplifier Architecture

In this paper, a low power, high linearity and high gain front-end circuit with novel LNA in 0.18 mu m CMOS technology for 5.2 GHz wireless applications is proposed. By employing current-bleeding and current-enhanced techniques, the conversion gain and the linearity can be increased and the power consumption is reduced. The complementary common-gate LNA is adopted to reduce noise and to improve linearity. With the LO power of 0 dBm, the proposed front-end circuit has conversion gain of 18.4 dB, input 1-dB compression point of -16 dBm and IIP3 of -6 dBm, while it consumes only 9.4mW. The chip size including pads is 0.767mm x 0.96mm.