Architectural synthesis of digital signal processing applications dedicated to submicron technologies

Architectural synthesis is an efficient design process that reduces the gap between algorithms and architectures by raising the abstraction level. However, this process currently does not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant using submicron technologies. In this paper, an interconnection cost analysis at the behavioural level is performed in order to provide rapid prototyping results and to direct the synthesis process with additional path constraints. Results are presented showing the interest of this approach.