Tunable floating and grounded memristor emulator model

被引:3
|
作者
Prasad, Sagar Surendra [1 ,4 ]
Dutta, Somenath [1 ]
Choubey, Chandan Kumar [2 ]
Dubey, Sanjay Kumar [3 ]
Priyadarshini, Bindu [3 ]
Ranjan, Rajeev Kumar [1 ,5 ]
机构
[1] Indian Inst Technol ISM, Dept Elect Engn, Dhanbad, India
[2] Symbiosis Int Univ, Symbiosis Inst Technol, Pune Campus, Pune, India
[3] K K Coll Engn & Management, Dept Elect & Commun Engn, Dhanbad, India
[4] ICFAI Fdn Higher Educ IFHE, Fac Sci & Technol IcfaiTech, Dept Elect & Commun Engn, Hyderabad, India
[5] Indian Inst Technol ISM, Dept Elect Engn, Dhanbad 826004, India
关键词
Memristor emulator (MRE); Current mode (CM); Differential difference current conveyor transconductance amplifier (DDCCTA); Pinched hysteresis loop (PHL); CIRCUIT; DEVICES;
D O I
10.1080/00207217.2023.2267218
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A Differential Difference Current Conveyor Transconductance Amplifier (DDCCTA) based resistor tunable memristor emulator has been proposed in this work. The emulator can be used in both grounded and floating circumstances. The proposed design incorporates only one active block along with few passive components. Moreover, the circuit can operate in both incremental and decremental modes, by simply changing the input ports. The circuit demonstrates all the characteristics of an ideal memristor up to 6 MHz. The proposed model has been simulated using TSMC 0.18$\mu $mu m process parameter and occupies an area of 51 x 42.5 $\mu $mu m2 chip-area, excluding capacitor. The circuit's reliability has been verified by studying non-ideal, non-volatile, Monte-Carlo, process corner variation analysis. The circuit applicability has been tested through series/parallel combinations. To validate the experimental demonstration, AD844AN and CA3080 have been used to make a prototype, which shows good agreement with theoretical and simulation results.
引用
收藏
页数:18
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