Improved frequency compensation technique of three stage amplifier using class AB flipped voltage follower and slew rate enhancer circuit

In this work, two frequency compensated three stage amplifiers are proposed for 20 pF and 30 pF capacitive load. Both the proposed circuits utilize class AB Flipped Voltage Follower (FVF) along with Reversed Nested Miller Compensation (RNMC) to address RHP zero issue. Further, the proposed circuits 1 and 2 employ a slew rate enhancer circuit to improve the slew rate. Additionally, both the circuits also make use of feed forward path to increase the large signal response. The simulations are performed using TSMC 0.18 mu m CMOS process in Tanner tool to examine the functionality and performance of the proposed amplifiers. The proposed amplifiers exhibit GBW of 25 MHz with phase margin of 82 at 20 pF load, whereas it is 22 MHz with phase margin of 79 at 30 pF load. Moreover, DC gain is 102 dB and 110 dB for the proposed amplifier-1 and 2 respectively. Further, maximum slew rate is 10.8 V/mu S at 20 pF load while it is 10.56 V/mu S at 30 pF load. The maximum common mode rejection ratio and power supply rejection ratio are examined to be 87.8 dB and 87.4 dB respectively. Corner analysis has been performed to look into the process variations to verify the robustness of the proposed amplifiers.