Tunable voltage polarity-dependent resistive switching characteristics by interface energy barrier modulation in ceria-based bilayer memristors for neuromorphic computing

Synaptic characteristics with tunable dependence on the voltage polarity are demonstrated in ceria (CeO2) and Gd-doped ceria (GDC) bilayer memristors with respect to their stacking orders. Both Pt/GDC/CeO2/Pt and Pt/ CeO2/GDC/Pt memristors with different oxide stacking orders exhibit analog, linear, and symmetric synaptic weights for potentiation and depression, paired-pulse facilitation, and short- and long-term plasticity (STP and LTP, respectively). Potentiation and depression behaviors are highly linear and symmetric thanks to the stacking of more oxygen-deficient GDC layer with CeO2, which facilitates the redistribution of oxygen vacancies for analog resistance change. These memristors have opposite dependence of synaptic weight updates on the polarity of potentiation and depression voltages for the stacking order of CeO2 and GDC, which are consistently interpreted by voltage-driven energy barrier modulation at the interface between CeO2 and GDC or with Pt electrodes via oxygen vacancy redistribution. Recognition simulation with modified handwritten digits patterns using a two-layer perceptron neural network exhibits accuracy of approximately 88% with achieved dynamic range, linearity, symmetry, and precision states. These synaptic characteristics are also demonstrated in a 32 x 32 crossbar array of GDC-top memristors. This verifies the potential of bilayer memristors for application in artificial synapse networks in neuromorphic computing systems.