Design and implementation for a high-efficiency hardware accelerator to realize the learning machine for predicting OLED degradation

被引:3
|
作者
Chang, I. -Feng [1 ]
Chen, Hao-Ren [1 ]
Chao, Paul C. -P. [1 ]
机构
[1] Natl Yang Ming Chiao Tung Univ, Dept Elect & Elect Engn, Hsinchu 300, Taiwan
关键词
NEURAL-NETWORK;
D O I
10.1007/s00542-023-05442-9
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new learning machine based on neural network (NN) and its hardware accelerator are successfully built in this study for predicting the luminance decay of Organic Light Emitting Diode (OLED) displays. It is known that although OLED displays has become the mainstream in the current high-end display market, OLEDs tend to degrade in emission as used extensively for a long time. The operable voltage also rises with the usage time increasing, which causes the operating point to drift. To compensate the OLED degradation, a NN model is successfully built with favorable accuracy. Furthermore, the built NN model is implemented in FPGA hardware platform with a high-performance computing architecture, which uses registers to access inputs, integrates the multiplication, addition operations for weights and activation function into the same combinational logic circuit, and a pipeline architecture to improve maximum operation per unit time. The hardware architecture is designed via Verilog, and further verified by Xilinx Artix-7. Its operating frequency can be as high as 55.6 MHz, while resource consumption is only 1.0k LUTs, favorable as opposed to all the other past, related studies. Experiment shows that the computation of the built NN by the proposed accelerator can be completed 55.6 million times per second. In addition, the degradation prediction errors by the accelerator are as small as 2.08%, 5.51% and 4.36% for red, green and blue OLEDs, respectively, while the figure of merit, the product of computation time and area is as low as 109.86 (Time*Area), the lowest compared to all the past reported works.
引用
收藏
页码:1069 / 1081
页数:13
相关论文
共 50 条
  • [1] Design and implementation for a high-efficiency hardware accelerator to realize the learning machine for predicting OLED degradation
    I.-Feng Chang
    Hao-Ren Chen
    Paul C.-P. Chao
    [J]. Microsystem Technologies, 2023, 29 : 1069 - 1081
  • [2] Hardware design and implementation of high-efficiency cube-root of complex numbers
    Rajaby, Elias
    Sayedi, Sayed Masoud
    Yazdian, Ehsan
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2023, 100
  • [3] DESIGN AND IMPLEMENTATION FOR THE HIGH EFFICIENCY HARDWARE ACCELERATOR APPLIED TO THE COMPENSATION OF IR DROP ON AMOLED PANEL
    Su, Tai-Chi
    Hsu, Jen-Yi
    Chao, Paul C. -P.
    [J]. PROCEEDINGS OF THE ASME 2023 32ND CONFERENCE ON INFORMATION STORAGE AND PROCESSING SYSTEMS, ISPS2023, 2023,
  • [4] High Throughput Hardware Implementation for Deep Learning AI Accelerator
    Wu, Chung-Bin
    Hsueh, Yu-Cheng
    Wang, Ching-Shun
    Lai, Yen-Chi
    [J]. 2019 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TW), 2019,
  • [5] Design of Target Recognition System Based on Machine Learning Hardware Accelerator
    Li, Yu
    Yu, Fengyuan
    Cai, Qian
    Qian, Meiyu
    Liu, Pengfeng
    Guo, Junwen
    Yan, Huan
    Yuan, Kun
    Yu, Juan
    [J]. WIRELESS PERSONAL COMMUNICATIONS, 2018, 102 (02) : 1557 - 1571
  • [6] Design of Target Recognition System Based on Machine Learning Hardware Accelerator
    Yu Li
    Fengyuan Yu
    Qian Cai
    Meiyu Qian
    Pengfeng Liu
    Junwen Guo
    Huan Yan
    Kun Yuan
    Juan Yu
    [J]. Wireless Personal Communications, 2018, 102 : 1557 - 1571
  • [7] Modular Design of High-Efficiency Hardware Median Filter Architecture
    Lin, Shih-Hsiang
    Chen, Pei-Yin
    Hsu, Chih-Kun
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65 (06) : 1929 - 1940
  • [8] Machine Learning Hardware Design for Efficiency, Flexibility, and Scalability [Feature]
    Zhang, Jie-Fang
    Zhang, Zhengya
    [J]. IEEE CIRCUITS AND SYSTEMS MAGAZINE, 2023, 23 (03) : 35 - 53
  • [9] Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction
    Chen, J.
    Lange, T.
    Andjelkovic, M.
    Simevski, A.
    Krstic, M.
    [J]. 2020 33RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2020,
  • [10] The Design and Implementation of a High-efficiency Distributed Web Crawler
    Pu, Qiumei
    [J]. 2016 IEEE 14TH INTL CONF ON DEPENDABLE, AUTONOMIC AND SECURE COMPUTING, 14TH INTL CONF ON PERVASIVE INTELLIGENCE AND COMPUTING, 2ND INTL CONF ON BIG DATA INTELLIGENCE AND COMPUTING AND CYBER SCIENCE AND TECHNOLOGY CONGRESS (DASC/PICOM/DATACOM/CYBERSC, 2016, : 100 - 104