Fixed-point implementations for feed-forward artificial neural networks

We present scalable and generalized fixed-point hardware designs (source VHDL code is provided) for Artificial Neural Networks (ANNs). Three architectures are presented: multiply-and-add, multiplier-less, fully pipelined. In addition, we include two approaches for ANN binary layers: accumulation-based and fully pipelined. The fully customized hardware architectures allow for design space exploration to establish trade-offs among numerical format, processing time, resource usage, and numerical accuracy. Users can select the ANN architecture, ANN parameters (structure, weights, biases), the numerical format for both the input/output data in every layer and the network parameters (weights and biases). Results are presented in terms of resources, processing time, and numerical accuracy. The proposed architectures were implemented on modern FPGAs. These hardware designs are expected to be used as building blocks on a variety of applications such as CNNs and SNNs, as well as a platform for educational purposes.