This paper proposes a 1st-order, error feedback (EF), sampling-rate (f(S)) reconfigurable Noise-Shaping Successive-Approximation-Register (NS-SAR) Analog-to-Digital-Converter (ADC) for multi-channel CMOS front-end ASICs for X-rays detectors in space applications. The core of the design is an 8-bits Asynchronous-SAR (ASAR) ADC, equipped with a unique variable rising-edge only delay-cell, which generates all required clock signals internally using a single external low duty-cycle sampling signal. The EF NS function has been achieved by introducing a 1st-order Finite-Impulse-Response (FIR) loop filter with a duty-cycled OP-AMP. Designed in a 0.35 mu m CMOS process at 3.3 V supply voltage, the proposed NS-SAR ADC achieves an ENOB of 11.8 bits and a peak SNDR of 72 dB at a typical f(S) of 40 kHz with an Oversampling-Ratio (OSR) of 8 in schematic-level simulations, consuming an average power of 37 mu W. The sampling frequency of the NS-SAR ADC is reconfigurable together with the power consumption while maintaining the same performance. For a fair comparison of the proposed high input signal swing (2 V) ADC at 3.3 V supply with low input signal swing ADCs at lower supply, normalized versions (FoM(WN), FoM(SN)) of FoM(W) and FoMS have been proposed. The ADC achieves its best FoM(WN) of 115.34 fJ/C-step and FoMSN of 186.31 dB at its maximum fS (178 kHz) at an OSR of 8.
