Unleashing SmartNIC Packet Processing Performance in P4

被引：6
|
作者：
Xing, Jiarong [1 ]
Qiu, Yiming [1 ]
Hsu, Kuo-Feng [2 ]
Sui, Songyuan [1 ]
Manaa, Khalid [3 ]
Shabtai, Omer [3 ]
Piasetzky, Yonatan [3 ]
Kadosh, Matty [3 ]
Krishnamurthy, Arvind [4 ]
Ng, T. S. Eugene [1 ]
Chen, Ang [1 ]
机构：
[1] Rice Univ, Houston, TX 77251 USA
[2] Meta, Menlo Pk, CA USA
[3] Nvidia, Santa Clara, CA USA
[4] Univ Washington, Seattle, WA 98195 USA
来源：
PROCEEDINGS OF THE 2023 ACM SIGCOMM 2023 CONFERENCE, SIGCOMM 2023 | 2023年
关键词：
SmartNICs; P4; Runtime Program Optimization;
D O I：
10.1145/3603269.3604882
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
SmartNICs are on the rise as a packet processing platform, with the trend towards a uniform P4 programming model. However, unleashing SmartNIC packet processing performance in P4 is a formidable task. Traditional SmartNIC optimizations rely on low-level program tuning, but P4 abstractions operate at one level above. At the same time, today's P4 optimizations primarily focus on resource packing rather than performance tuning. We develop Pipeleon, an automated performance optimization framework for P4 programmable SmartNICs. We introduce techniques that are tailored to the performance characteristics of SmartNICs, and further leverage dynamic workload patterns for profile-guided optimization. Pipeleon pinpoints program hotspots at the P4 level and computes runtime optimization plans to specialize the program layout based on the latest profile. We have prototyped Pipeleon and applied it to optimize two popular P4 SmartNICs-Nvidia BlueField2 and Netronome Agilio CX-as well as a software SmartNIC emulator extended based on BMv2. Our results show that Pipeleon significantly improves SmartNIC packet processing performance in realistic scenarios.
引用
收藏
页码：1028 / 1042
页数：15
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