Cyber Attack-Aware Security Hardening of Time Synchronization Technologies in WAMPAC Systems

Synchrophasor-based wide-area monitoring, protection, and control (WAMPAC) applications have been recently prevalent in modern power systems to counteract system-wide operational concerns. However, the functionality of the WAMPAC application is significantly contingent on the precision and integrity of time-synchronization mechanisms which are vulnerable to time-synchronization attacks (TSAs). To counter TSAs targeting WAMPAC applications, this paper proposes a preventive countermeasure by attack-aware security hardening of time synchronization technologies (TSTs) in substations houses critical phasor measurement units (PMUs). The attack-aware security hardening problem is formulated as a bi-level operator-attack model. This model aims to minimize post-TSA error of the PMU-based AC state estimation (ACSE), a critical module for a majority of WAMPAC applications, by optimal allocating a set of security hardening respecting the limited operator budget. The operator layer obtains security hardening strategy and under-TSA system states while the attacker layer optimizes attack vector and manipulated phasor measurements. Using the Karush-Kuhn-Tucker (KKT) approach, the developed model is recast to a single-level quadratic mixed-integer linear problem tackle-able using mathematical solvers. The numerical results on the IEEE 39-Bus test system demonstrate that the proposed preventive countermeasure can significantly reduce the attacker's ability to maliciously impact ACSE module.