Sign-Sign LMS-Based Adaptive DFE for 4PAM Multi-Gbps Serial Links

被引:0
|
作者
Altaee, Alaa R. [1 ]
机构
[1] Utah Valley Univ, Dept Elect & Comp Engn, Orem, UT 84058 USA
关键词
VLSI; Wire-line communication; Error detection; Timing Jitter; Adaptive DFE; CMOS Equalizer; Serial links; DECISION-FEEDBACK EQUALIZER;
D O I
10.1109/CCWC57344.2023.10099332
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, we present an adaptive decision feedback equalizer (ADFE) for multi-Gbps serial links utilizing a fix-step error signal extracted from cross-points of received data symbols. The extracted signal is generated based on the violation of received data symbols with minimum detection requirements at the signal-detection unit. The iterations of the adaptation process search for the optimum feedback tap coefficients to maximize the data eye-opening and minimize the adaptation convergence time. The validity of the proposed architecture is proved to utilize a serial link designed in an IBM 130 nm 1.2V CMOS technology. The data link with variable channel lengths is analyzed using Specter from Cadence Design Systems with BSIM4 device models.
引用
收藏
页码:923 / 927
页数:5
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