A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression

被引:1
|
作者
Dong, Yangtao [1 ]
Boon, Chirn Chye [1 ]
Liu, Zhe [1 ]
Yang, Kaituo [1 ]
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, VIRTUS, Singapore 639798, Singapore
基金
新加坡国家研究基金会;
关键词
CMOS phase-locked loop (PLL); dual-path architecture; high-pass filter (HPF); phase margin; phase noise suppression (PNS); ring voltage-controlled oscillator (VCO); subsampling phase detector (SSPD); SUB-SAMPLING PLL; JITTER; CMOS;
D O I
10.1109/TMTT.2023.3284279
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article presents a 2-GHz dual-path subsampling phase-locked loop (SSPLL) with ring voltage-controlled oscillator (VCO) phase noise suppression (PNS). In addition to the conventional subsampling charge pump (SSCP), a high-pass path from the subsampling phase detector (SSPD) to the low-pass filter (LPF) is implemented in the proposed SSPLL. Due to this dual-path architecture, a new in-band zero and pole are introduced into the open-loop transfer function (zero frequency is smaller than the pole frequency), which extends the open-loop unit-gain bandwidth without sacrificing the phase margin. Consequently, the phase noise contribution of the ring VCO is suppressed while the loop stability is ensured. Meanwhile, the phase noise contribution of the high-pass path is negligible compared to the reference and ring VCO's contribution. Measurement results show that the SSPLL's closed-loop bandwidth is extended to around 6 MHz with a reference of 20 MHz and the jitter is reduced by 1.34x (from 3.52 to 2.63 ps) with a maximum noise suppression of 6.5 dB at the 1.1-MHz offset. The PNS path consumes 0.16 mW and no delay line or calibration is needed, which results in a relatively high FoM(PNC) value of 40.5 dB.
引用
收藏
页码:138 / 148
页数:11
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