On-chip jitter BIST with sub-picosecond resolution at GHz frequencies

被引：0
|
作者：
Madhvaraj, Manasa [1 ]
Mir, Salvador [1 ]
Barragan, Manuel J. [1 ]
机构：
[1] Univ Grenoble Alpes, CNRS, Grenoble INP, TIMA, F-38000 Grenoble, France
来源：
2023 IEEE 24TH LATIN AMERICAN TEST SYMPOSIUM, LATS | 2023年
关键词：
MEASUREMENT CIRCUIT; CLOCK;
D O I：
10.1109/LATS58125.2023.10154493
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
This paper describes an on-chip instrument for jitter estimation of clock signals in the GHz range with a sub-picosecond resolution. A self-referenced technique is used to remove the need of a very clean external reference clock. The instrument has been designed in STMicroelectronics 28nm FDSOI technology. By exploiting the fine delay control which can be achieved with this technology, simulation results haven shown a resolution down to 100 fs for GHz clock signals with a simple calibration procedure.
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页数：2
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