Algorithm-Aware Digital Design for Analog-on-Top Chips: an ASK Demodulator Comparative Study

被引：0

作者：

Tecce, Felice ^{[1
]}

Abate, Matteo ^{[1
]}

Del Prete, Francesco ^{[1
]}

Cirillo, Giovanni Amedeo ^{[2
]}

Parrella, Claudio ^{[1
]}

Castellano, Marco ^{[2
]}

机构：

[1] STMicroelectronics, AMS R&D, Arzano, NA, Italy

[2] STMicroelectronics, AMS R&D, Cornaredo, MI, Italy

来源：

2023 IEEE SENSORS | 2023年

关键词：

IP digital design; High-Level Synthesis; High-Language Hardware; Hardware Description Language; Catapult; SpinalHDL; SystemVerilog; Amplitude Shift Keying;

D O I：

10.1109/SENSORS56945.2023.10325037

中图分类号：

R318 [生物医学工程];

学科分类号：

0831 ;

摘要：

Design of application-specific Digital Signal Processing elements is related to the implementation of an algorithm, initially implemented in software. The time-to-design can be extremely long, especially when design space exploration must be done and hardware description must be written from scratch. Different tools are nowadays available to generate a Register Transfer Level (RTL) circuit and corresponding testbenches from software, even with routines for design space exploration. These tools are based on High-Level Synthesis (HLS) and High-Language Hardware description (HLH) paradigms. This work compares the RTLs for an integrated digital Amplitude Shift Keying demodulator, employable either for the recognition of messages detected by transducers or in sensors networks. SystemVerilog, Catapult HLS from Siemens EDA and SpinalHDL were considered for canonical hardware description, HLS and HLH respectively. Synthesis results with three STMicroelectronics technologies prove that the RTLs automatically generated by SpinalHDL and Catapult provide area results comparable with those obtained with from-scratch design in SystemVerilog and can also achieve better performance in terms of dynamic power.

引用

页数：4