A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier

This article presents a 13-b high-speed pipelinedsuccessive-approximation-register (pipelined-SAR) analogto-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process. The tri-state SAR outputs three states by one comparator after each comparison cycle, and the effective-number-of-bits (ENOBs) can improve up to 1 b when the metastability boundary is set at +/- 1/4 LSB. In addition, an open-loop inverter-based residue amplifier (RA) is proposed with simple circuit implementation. The RA gain is well defined by g(m) ratio and is immune to process, voltage, and temperature (PVT) variations. Fabricated in 40-nm CMOS technology, the prototype ADC achieves a mean signal-to-noise plus distortion ratio (SNDR) of 59.8-62.8 dB, with 1-sigma than 1.7 dB, at 600-625 MS/s over -40 degrees to 125 degrees temperature range and 1.1-1.2 V power supply range, a 67 dB dynamic range (DR), and a 62.4 dB SNDR for a Nyquist input while sampling at 625 MS/s. The overall power consumption is 7.05 mW.