Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design

Adaptive filtering plays an essential role in digital signal processing (DSP), being present in many application fields such as noise reduction, telecommunication, and audio signal processing. Notably, the least mean square (LMS) and its normalized version (NLMS) are the most used algorithms due to their simplicity and robustness, which turn them attractive to hardware solutions. This work proposes architectural solutions for LMS and NLMS algorithms targeting an energy-efficient VLSI design. We explore fully sequential, fully parallel, and semi-parallel architectures reusing the hardware as much as possible for both algorithms. It allows for investigating the number of steps necessary for each architecture, demonstrating the energy per operation, circuit area, and throughput savings. The synthesis results highlight the semi-parallel architectures LMS-2 steps and NLMS-3 steps have the best trade-off energy-speed. In addition, we proved the architecture's energy efficiency in a harmonic canceling case study, achieving more than 60% in energy savings using both filters.