Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator

This paper presents a design and an implementation of an on-line quality control method for a TRNG (True Random Number Gener-ator) on an FPGA. It is based on a TRNG with RS latches and a temporal XOR corrector, which can make a trade-off between throughput and ran-domness quality by changing the number of accumulations by XOR. The goal of our method is to increase the throughput within the range of keep-ing the quality of output random numbers. In order to detect a sign of the loss of quality from the TRNG in parallel with random number generation, our method distinguishes random bitstrings to be tested from those to be output. The test bitstring is generated with the fewer number of accumu-lations than that of the output bitstring. The number of accumulations will increased if the test bitstring fails in the randomness test. We designed and evaluated a prototype of on-line quality control system, using a Zynq- 7000 FPGA SoC. The results indicate that the TRNG with the proposed method achieved 1.91-2.63 Mbits/s of throughput with 16 latches, follow-ing the change of the quality of output random numbers. The total number logic elements in the prototype system with 16 latches was comparable an with 256 latches, without control