Application Specific Reconfigurable Processor for Eyeblink Detection from Dual-Channel EOG Signal

被引:1
|
作者
Das, Diba [1 ]
Chowdhury, Mehdi Hasan [1 ]
Chowdhury, Aditta [1 ]
Hasan, Kamrul [1 ]
Hossain, Quazi Delwar [1 ]
Cheung, Ray C. C. [2 ]
机构
[1] Chittagong Univ Engn & Technol, Dept Elect & Elect Engn, Chattogram 4349, Bangladesh
[2] City Univ Hong Kong, Dept Elect Engn, Kowloon, Hong Kong, Peoples R China
关键词
blink; classification; electrooculogram (EOG); field-programmable gate array (FPGA); machine learning; saccade; support vector machine (SVM); EYE BLINK; EEG; CLASSIFICATION; ELIMINATION; ALGORITHM; SYSTEM;
D O I
10.3390/jlpea13040061
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The electrooculogram (EOG) is one of the most significant signals carrying eye movement information, such as blinks and saccades. There are many human-computer interface (HCI) applications based on eye blinks. For example, the detection of eye blinks can be useful for paralyzed people in controlling wheelchairs. Eye blink features from EOG signals can be useful in drowsiness detection. In some applications of electroencephalograms (EEGs), eye blinks are considered noise. The accurate detection of eye blinks can help achieve denoised EEG signals. In this paper, we aimed to design an application-specific reconfigurable binary EOG signal processor to classify blinks and saccades. This work used dual-channel EOG signals containing horizontal and vertical EOG signals. At first, the EOG signals were preprocessed, and then, by extracting only two features, the root mean square (RMS) and standard deviation (STD), blink and saccades were classified. In the classification stage, 97.5% accuracy was obtained using a support vector machine (SVM) at the simulation level. Further, we implemented the system on Xilinx Zynq-7000 FPGAs by hardware/software co-design. The processing was entirely carried out using a hybrid serial-parallel technique for low-power hardware optimization. The overall hardware accuracy for detecting blinks was 95%. The on-chip power consumption for this design was 0.8 watts, whereas the dynamic power was 0.684 watts (86%), and the static power was 0.116 watts (14%).
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页数:16
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