Semantic Segmentation-Based Wafer Map Mixed-Type Defect Pattern Recognition

被引:6
|
作者
Yan, Jinda [1 ]
Sheng, Yi [1 ]
Piao, Minghao [1 ]
机构
[1] Soochow Univ, Sch Comp Sci & Technol, Suzhou 215006, Jiangsu, Peoples R China
关键词
Pattern recognition; Semantic segmentation; Semiconductor device modeling; Convolutional neural networks; Semantics; Neural networks; Labeling; Defect detection; mixed-type patterns; pattern recognition; semantic segmentation; CLASSIFICATION;
D O I
10.1109/TCAD.2023.3274958
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Recent research applying deep learning to the field of defect pattern recognition in wafer maps has greatly accelerated the process of defect detection. However, when different defects are mixed on the same wafer, the mixed type is very complex, and it is still difficult to recognize the defect pattern. In this article, we propose a new framework to segment different defect patterns on the wafer map by using a semantic segmentation approach. This method works well on single and known and unknown mixed types. First, we extract the defects from the single-defect wafer map of the MixedWM38 dataset to generate single-defect pixel-level labels. Then, a mixed defect pattern dataset suitable for semantic segmentation is generated using single-defect wafer maps and single-defect pixel-level labels. The average accuracy of the test set on our synthetic dataset reaches over 97%, and using the trained model for testing on MixedWM38, we can get an average accuracy of 95.8%.
引用
收藏
页码:4065 / 4074
页数:10
相关论文
共 50 条
  • [1] An efficient deep learning framework for mixed-type wafer map defect pattern recognition
    Sheng, Hao
    Cheng, Kun
    Jin, Xiaokang
    Jiang, Xiaolin
    Dong, Changchun
    Han, Tian
    AIP ADVANCES, 2024, 14 (04)
  • [2] Mixed-Type Wafer Defect Pattern Recognition Framework Based on Multifaceted Dynamic Convolution
    Wei, Yuxiang
    Wang, Huan
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2022, 71
  • [3] Mixed-type defect pattern recognition in noisy labeled wafer bin maps
    Kim, Sumin
    Kim, Heeyoung
    QUALITY ENGINEERING, 2023,
  • [4] Deformable Convolutional Networks for Efficient Mixed-Type Wafer Defect Pattern Recognition
    Wang, Junliang
    Xu, Chuqiao
    Yang, Zhengliang
    Zhang, Jie
    Li, Xiaoou
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2020, 33 (04) : 587 - 596
  • [5] Efficient Mixed-Type Wafer Defect Pattern Recognition Based on Light-Weight Neural Network
    Deng, Guangyuan
    Wang, Hongcheng
    MICROMACHINES, 2024, 15 (07)
  • [6] Mixed-Type Wafer Failure Pattern Recognition (Invited Paper)
    Geng, Hao
    Sun, Qi
    Chen, Tinghuan
    Xu, Qi
    Ho, Tsung-Yi
    Yu, Bei
    2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC, 2023, : 727 - 732
  • [7] Contrastive Learning with Global and Local Representation for Mixed-Type Wafer Defect Recognition
    Yin, Shantong
    Zhang, Yangkun
    Wang, Rui
    SENSORS, 2025, 25 (04)
  • [8] Recognition and Classification of Mixed Defect Pattern Wafer Map Based on Multi-Path DCNN
    Hou, Xingna
    Yi, Mulan
    Chen, Shouhong
    Liu, Meiqi
    Zhu, Ziren
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2024, 37 (03) : 316 - 328
  • [9] PoLM: Point Cloud and Large Pre-trained Model Catch Mixed-type Wafer Defect Pattern Recognition
    He, Hongquan
    Kuang, Guowen
    Sun, Qi
    Geng, Hao
    2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE, 2024,
  • [10] Mixed-Type Wafer Defect Recognition With Multi-Scale Information Fusion Transformer
    Wei, Yuxiang
    Wang, Huan
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2022, 35 (02) : 341 - 352